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CS2082 Dual Airbag Deployment ASIC
The CS2082 controls and monitors two airbag firing loops. The independent firing loops are low- and high-side controlled. Device communication is through a Serial Peripheral Interface (SPI) port, and includes frame error detection circuitry for data reliability. Diagnostics include squib resistance measurement and continuous monitoring for shorts to ground, shorts to battery, and for open loops. The high- and low-side drivers can be individually activated to guarantee function and to identify shorts between firing loops. Additional features include power on reset, overtemperature protection, a charge pump, high-side safing sensor closure detection, an analog multiplexer, a monitor to ensure battery potential, and a programmable monitor to ensure firing potential. Features * Serial Input Bus * Two Squib Outputs * Low- and High-Side Control * Monitors - Squib Resistance - Short to Ground or Battery - Battery Potential - Firing Potential * Safing Sensor Detection * 60 V Peak Transient Voltage
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SO-20L DW SUFFIX CASE 751D
PIN CONNECTIONS AND MARKING DIAGRAM
1 VBAT CHRG VRES VR1 SH1 SL1 FG1 DOUT CLK MR A WL, L YY, Y WW, W 20 GND VCC DIN VR2 SH2 SL2 FG2 AIN AOUT CS
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device CS2082EDW20 CS2082EDWR20 Package SO-20L SO-20L Shipping 37 Units/Rail 1000 Tape & Reel
CS2082 AWLYYWW
(c) Semiconductor Components Industries, LLC, 2001
1
July, 2001 - Rev. 7
Publication Order Number: CS2082/D
CS2082
CHRG VCC VRES VBAT Battery Monitor VRES Monitor Charge Pump Monitor Charge Pump Sensor Monitor VR1 1.5 VBAT 10 k SH1 VRES 2R SPI + - R Diagnostic Gate Drive Current Limit Overtemperature Reset VCC CHRG Gate Drive
1
CHRG Gate Drive
VBAT R + -
1 2
Current Limit
1.5 10 k
SL1
FG1 GND 1.5 VBAT 10 k SH2 VR2
VBAT
Current Limit - +
2
+ 50 mV
Current Limit
Analog MUX VCC
VRES Resistive Measurement Gate Drive Current Limit
1.5 10 k
SL2
FG2
CS CLK DIN DOUT AIN AOUT MR
Figure 1. Block Diagram
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MAXIMUM RATINGS*
Rating Storage Temperature VBAT VRES VCC ESD Susceptibility (Human Body Model) Power Dissipation (Non-Firing) Power Dissipation (Both Firing Loops With Squibs Shorted) Power Dissipation (Squib Resistance Measurement) Peak Transient Voltage (46 V Load Dump @ 14 V VBAT) Lead Temperature Soldering: 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1) Value -40 to 150 -0.3 to 24 -0.3 to 30 -0.3 to 6.0 500 0.15 140 1.6 60 230 peak Unit C V V V V W W W V C
ELECTRICAL CHARACTERISTICS (4.75 V < VCC < 5.25 V, 8.0 V < VRES < 30 V, 9.0 V < VBAT < 18 V, -40C < TA < +85C; unless otherwise stated.)
Parameter Supply Requirements VCC Quiescent Current VBAT Quiescent Current VBAT Measurement Current VRES Quiescent Current VRES Firing Current Power on Reset Power Reset Active Voltage Power Reset Off Voltage Hysteresis Low Side Driver Saturation Voltage Current Limit (ILIMIT) Turn-on Delay Time Turn-off Delay Time High Side Driver Saturation Voltage Current Limit (ILIMIT) VR1 Quiescent Current Drivers off VR2 Quiescent Current Drivers off Turn-on Delay Time Turn-off Delay Time Thermal Shut Down Thermal Shutdown Temp Thermal Hysteresis Guaranteed by Design Guaranteed by Design 150 30 180 40 210 60 C C VCC = 5.25 V VBAT = 18 V VBAT = 18 V, RSQUIB = 1.0 VRES = 30 V VRES = 30 V VBAT = 9.0 V, VRES = 10 V VCC Falling VCC Rising - VRES = 8.0 V = VRX, VCC = 5.0 V, VBAT = 8.0 V I = 1.2 A VSLX - VFGX = 5.0 V From CS falling Edge, ID = 0.9 x ILIMIT(MIN) From CS falling Edge, ID = 0.1 x ILIMIT(MIN) VRES = 8.0 V = VRX, VCC = 5.0 V, VBAT = 8.0 V I = 1.2 A VRX - VSHX = 5.0 V VRX = VRES = 30 V VRX = VRES = 30 V From CS falling Edge, ID = 0.9 x ILIMIT(MIN) From CS falling Edge, ID = 0.1 x ILIMIT(MIN) - 1.2 - - - - - 2.0 - - - - 1.8 2.5 1.0 100 100 25 V A mA A s s - 1.2 - - - 1.6 - - 1.8 2.0 75 25 V A s s 3.50 3.65 50 4.00 4.20 - 4.25 4.50 - V V mV - - - - - 2.0 2.5 - - - 4.0 5.0 80 1.0 3.0 mA mA mA mA mA Test Conditions Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS (continued) (4.75 V < VCC < 5.25 V, 8.0 V < VRES < 30 V, 9.0 V < VBAT < 18 V,
-40C < TA < +85C; unless otherwise stated.) Parameter Thermal Shut Down Time to Thermal Shutdown Squib Resistive Measurements Squib Differential Voltage Difference Between SHx & MR current - SHx reference SHx Current Limit SLx Current Limit MR Voltage Clamp Turn On Delay Time excluding external Capacitors Turn off Delay Time Short Measurements SHx pull-up resistance to VBAT SLx pull-down resistance Pull-up resistor matching Pull-down resistor matching Short to VBAT Trip Short to GND Trip VBAT Monitoring VBAT Low Trip VBAT High Trip VRES Monitoring VRES Low Trip VRES High Trip VRES Low Trip VRES High Trip Safing Sensor Monitor External Resistance Trip Range Charge Pump and Monitor Oscillator Frequency Charge Pump charge time Charge Pump Low Voltage Charge Pump High Voltage Analog MUX AOUT Output Range AIN Input Range SSC bit set when resistance is less VCC = 5.0 V, VBAT = 10 V VRES = 10 V CCHG = 0.1 F, VRES = 8.0 V, Chrg from 8.0 V to 14 V CL bit set to 1 when below trip CL bit set to 0 when above trip VCC = 5.0 V - - 0.1 0 - - VCC - 0.1 VCC V V 200 - 14.5 15.0 - - 16.0 17.5 800 20 17.5 18.0 kHz ms V V 30 400 600 SHx short to Battery SLx bit set to 1 SHx short to GND SGx bit set to 1 RSQUIB = 0, VRX = 30 V, T = 85C, Guaranteed by Design VCC = 5.0 V, RMR = 49.9 W, VRES = 30 V VDIFF = SHx - SLx, RSQUIB = 1.0 to 10 ISQUIB = 50 mA RSQUIB = 0 RMR = 0 - - - VCC = 5.0 V, VRES . VBAT, VRX . VBAT VBAT = 18 V - - 4.0 4.0 -5.0 -5.0 0.73 x VBAT 0.23 x VBAT 10 10 - - 0.75 x VBAT 0.25 x VBAT 17 17 5.0 5.0 0.77 x VBAT 0.27 x VBAT k k % % V V 46 -1.0 67 77 VCC - 0.3 - - 53 - 100 115 - - - 60 1.0 133 153 VCC + 0.3 100 50 mV % mA mA V s s 7.0 - - ms Test Conditions Min Typ Max Unit
VCC = 5.0 V, External VBAT Diode not included, VRES = 30 V BL bit set to 1 when below trip BL bit set to 0 when above trip VCC = 5.0 V, VBAT = 18 V $6d AUX register b0 = 0 $6d AUX register b0 = 0 $6d AUX register b0 = 1 $6d AUX register b0 = 1 15.7 16.5 21.5 22.5 17.5 18.5 24.0 25 19.3 20.5 26.5 27.5 V V V V 7.5 8.0 8.5 9.0 9.5 10 V V
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ELECTRICAL CHARACTERISTICS (continued) (4.75 V < VCC < 5.25 V, 8.0 V < VRES < 30 V, 9.0 V < VBAT < 18 V,
-40C < TA < +85C; unless otherwise stated.) Parameter Analog MUX MUX internal voltage drop Proportion of VBAT on AOUT with VBAT selected AOUT Impedance with VBAT selected Proportion of VRES on AOUT with VRES selected AOUT Impedance with VRES selected Digital Inputs - DIN, CLK, CS Input Low Voltage (VIL) Input High Voltage (VIH) Input Voltage Hysteresis Input Pull Down Current (IIH) Digital Outputs - DOUT Output Low Voltage (VOL) Output High Voltage (VOH) Tri-State Pull-up Current Rise | Fall Time VCC = 5.0 V IOUT = 100 A - - - - VCC = 5.25 V, VBAT = 18 V, VRES = 30 V - - - - VCC = 4.75 V, VBAT = 18 V, VRES = 30 V ISINK = 1.0 mA ISOURCE = 1.0 mA CS = 0, DOUT = 0 CLOAD = 200 pF - VCC - 0.75 50 - - - 100 - 0.4 - 200 50 V V A ns 0 0.7 x VCC 100 50 - - - 100 0.3 x VCC VCC - 200 V V mV A - 23 6.0 15 6.0 - 25 15.0 17 12.5 100 27 35 19 25.5 mV % k % k Test Conditions Min Typ Max Unit
PACKAGE PIN DESCRIPTION
Package Lead Number SO-20L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pin Symbol VBAT CHRG VRES VR1 SH1 SL1 FG1 DOUT CLK MR CS AOUT AIN FG2 SL2 SH2 VR2 Battery Supply Voltage. Charge pump Storage. Reserve Supply Voltage. Loop 1 Supply. Squib 1 High Side. Squib 1 Low Side. Loop 1 Return. Serial Port output. Serial Port Clock. Squib Resistance Output Current. Serial Port Chip Select. Analog MUX Output. Analog MUX Input. Loop 2 Return. Squib 2 Low Side. Squib 2 High Side. Loop 2 Supply. Function
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PACKAGE PIN DESCRIPTION (continued)
Package Lead Number SO-20L 18 19 20 Pin Symbol DIN VCC GND Serial Port Input. 5.0 V Regulated Supply. Signal Ground. Function
FUNCTIONAL DESCRIPTION The CS2082 is an automotive air bag deployment and diagnostic system for up to two independent firing loops. Communication with the ASIC is through a synchronous serial port using Serial Peripheral Interface (SPI) protocol, at CLK rates up to 2.0 MHz. Data is simultaneously sent from the DOUT pin and received at the DIN pin under the control of the CS and CLK pins. Error detection logic is included in the SPI to guard against glitches on either the CS or CLK logic signal inputs. A valid CS frame must contain exactly 8 CLK cycles for each CS low-high-low transition. Detection of a frame error will cause input data for that frame to be ignored and an error code ($FE) to be sent during the next valid CS frame. The data at DOUT is sent MSB first and is guaranteed valid before the rising edge of CLK. The 8 bits sent from DOUT after CS goes high will be the previous data received, data from either the status register or the fault register, or the CS frame error code ($FE). The data at DIN is received MSB first and must be valid before the rising edge of CLK. The 8 bits received at DIN before CS goes low will be the current command. Table 1 defines the legal 8-bit SPI commands, where d = four data bits and x = don't care. All other inputs will be ignored.
Table 1. Valid CS2082 SPI Commands
COMMAND $1x $2x $3d $4d $5d $6d $Ad FUNCTION Read Staus Register Read Fault Register Squib Resistance Measurements Analog MUX Select Low Side Switch Control Auxiliary Control Register High Side Switch Control BIT D7 D6 D5 D4 D3 D2 D1 D0
the VRES and VR1 pins, the state of the internal charge pump, and the state of external VBAT and VRES power supplies. The status register is an 8-bit active-high register with bit definition as shown in Table 2.
Table 2. Status Register Bit Definition
BIT D7 D6 D5 D4 D3 D2 D1 D0 VALUE 0 0 F1 F2 SSC RL BL CL DESCRIPTION Always Logic zero Always Logic zero SH1 and SL1 switches active SH2 and SL2 switches active Safing Sensor is closed VRES voltage is below trip VBAT voltage is below trip CHRG voltage is below trip
Read Fault Register - $2x
The $2x command causes the data contained in the fault register to be sent from DOUT during the next valid CS frame. The register reports fire path faults by continuously comparing each path to a portion of the voltage at the VBAT pin. The fault register is an 8-bit active-high register with bit definition as shown in Table 3.
Table 3. Fault Register Bit Definition
VALUE 0 0 0 0 SB2 SB1 SG2 SG1 DESCRIPTION Always Logic zero Always Logic zero Always Logic zero Always Logic zero High Side of Sqib 2 above 75% VBAT trip threshold High Side of Sqib 1 above 75% VBAT trip threshold Low Side of Sqib 2 below 25% VBAT trip threshold Low Side of Sqib 1 below 25% VBAT trip threshold
Read Status Register - $1x
The $1x command causes the data contained in the status register to be sent from DOUT during the next valid CS frame. The status register reports the condition of the firing paths, closure detection of an external safing switch between
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Each SHx pin is pulled up to VBAT while each SLx pin is pulled down to GND through separate nominal 10 k resistors, thus biasing each normal fire path to about 1/2 VBAT. An open fire path has been detected if both the SBx and SGx bits are set for that path. To detect faults between fire paths and to test driver function, each driver should be activated individually. The activated driver should cause its respective fault bit to be set. If an activated driver does not set its respective fault bit, a driver fault has been detected. If an activated driver causes the fault bit of an inactivated driver to be set, a fault between fire paths has been detected. Table 4 defines the implied ranges over which the various types of faults can be detected.
Table 4. Implied Resistive Fault Detection Ranges
Fault Short to Ground Short to Battery Open Driver Open Driver Shorted Squib to Squib Min 1 1 5 1 1 1 Nom 5 5 20 5 5 5 Max 10 10 40 10 10 10 Unit k k k k k k 4.5 4.0 3.5 3.0 VMR 2.5 2.0 1.5 1.0 0.5 0 0.6 1.4 2.2 3.0 3.8 RSQUIB 4.6 5.4
Figure 2. Typical MR Voltage Response
Measurement accuracy of the CS2082 with combined tolerances and with and external 1% load resistor at the MR pin can be defined by the equation:
RSQ(E) + VDIFF(IDEAL)
VDIFF"12% RSQ(A)
RMR(IDEAL) RMR " 1%
" 1%
+ RSQ(A))12.5% *15.94%
Squib Resistance Measurement - $3d
The $3d command activates squib resistance measurement for the selected firing path. The respective active-high bit definitions are shown in Table 5. At power-up, the default path is `None.'
Table 5. Squib Resistance Path Select
D3 x x x x D2 x x x x D1 0 0 1 1 D0 0 1 0 1 NONE SQUIB 1 SQUIB 2 NONE Path
where VDIFF(IDEAL) and RMR(IDEAL) are the assumed values for the squib resistance solution algorithm, RSQ(A) is the actual squib resistance, and RSQ(E) is the result of the solution algorithm. An additional error may be added if the MR voltage is measured through the analog multiplexer. In operation, current is sourced from VBAT to the SHx pin, through the squib to the SLx pin, and returned to ground through the MR load resistor. Current clamps are provided for both the SHx and SLx pins and a voltage clamp is provided for the MR pin. These clamps along with the resolution of the ADC are the constraining factors for the minimum and maximum measurable squib resistance values. The minimum measurable squib resistance can be defined as:
VDIFF(MIN) VDIFF(MIN) RMR(MIN) v RSQUIB(MIN) v ILIM(MAX) VCLAMP(MAX)
Squib resistance is measured by forcing 50 mV nominal (proportional to VCC) across the squib. The resulting squib current is passed to an external load resistor at the MR pin, converting the current back into a voltage. This voltage may be read directly at the MR pin, or passed through the analog multiplexer to be read at the AOUT pin. The known values of the squib differential voltage (VDIFF) and the MR resistance (RMR), and the measured MR voltage (VMR) indicate squib resistance such that:
RSQUIB + RMR VDIFF VMR
The maximum measurable squib resistance can be defined as:
RSQUIB(MAX) + VDIFF(MAX) RMR(MAX) VCC(MIN) (2n * 1)
Typical MR voltage response for RMR = 50 over a squib resistance range of 0.6 to 6.0 is illustrated in Figure 2.
In the above equations, VDIFF is the SHx-SLx forced differential voltage, ILIM is the SHx resistive measure current limit, VCLAMP is the MR clamp voltage, RMR is the toleranced MR load resistor value and n is the number of bits of resolution of the ADC. It should be noted that during resistive measurements, faults to GND or BAT (dependent on VBAT voltage and
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CS2082
squib resistance) may be reported by the fault register and should be ignored. Power Dissipation during resistive measurement can be calculated as:
P + ISQUIB(VBAT * VDIFF) * (ISQUIB RMR) Table 7. Low Side Switch Select
D3 x x x x D2 x x x x D1 0 0 1 1 D0 0 1 0 1 BOTH SL2 SL1 NONE Active
where VBAT is the voltage at the CS2082 VBAT pin and ISQUIB is the measurement current through the squib. A typical value for P is 300 mW when VBAT = 13.5, VDIFF = 50 mV, RSQUIB = 2.0 and RMR = 49.9 . The resultant increase in power dissipation will cause a corresponding increase in die temperature which will cause a corresponding decrease in time to thermal shutdown of the CS2082. To minimize the impact of squib resistive measurements on time to thermal shutdown a 5% duty cycle is recommended.
Analog MUX - $4d
Auxiliary Control Register - $6d
The $6d command selects the VRES Monitoring trip threshold. The threshold determines when the $1x Status Register reports VRES = 1. Bit assignment is shown in Table 8. At power-up, default trip is 17 V.
Table 8. VRES Monitor Trip Select
D3 x x D2 x x D1 x x D0 0 1 17 V 23 V Trip
The $4d command selects one of five states at the AOUT pin. The states are: High-Z; MR voltage; AIN voltage; proportion of VBAT; proportion of VRES. The active-high Analog Mux select register bit definitions are shown in Table 6. All other states will be interpreted as High-Z. At power-up, the default state is `High-Z.'
Table 6. Analog MUX Output Select
D3 0 0 0 0 1 D2 0 0 0 1 0 D1 0 0 1 0 0 D0 0 1 0 0 0 High-Z MR AIN BAT RES State
High Side Switch Control - $Ad
The $Ad command activates the high side switches. When a data bit is high, that switch is turned on. More than one switch can be activated at a time. Bit assignment is shown in Table 9. Note that the $5d and $Ad commands are binary complements, i.e., by sending 1010xx11, both high side switches are activated, and by sending the complement 0101xx00, both low side switches are activated. At power-up, no switches are active.
Table 9. High Side Switch Select
D3 x x D2 x x x x D1 0 0 1 1 D0 0 1 0 1 NONE SH1 SH2 BOTH Active
Low Side Switch Control - $5d
x x
The $5d command activates the low side switches. When a data bit is low that switch is turned on. More than one switch can be activated at a time. Bit assignment is shown in Table 7. At power-up, no switches are active.
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VIGN VBOOST VCC
VBAT CHRG VRES VR1
CRES CCM CDM CCM
GND VCC DIN VR2 CS2082 SH2 SL2 FG2 AIN AOUT CS
Analog Input CCM CDM CCM
+
SH1 SL1 FG1 DOUT CLK MR
+
CRES
CMR
MCU
Figure 3. Application Diagram
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PACKAGE DIMENSIONS
SO-20L DW SUFFIX CASE 751D-05 ISSUE F
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical SO-20L 17 90 Unit C/W C/W
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L
CS2082
Notes
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PUBLICATION ORDERING INFORMATION
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CS2082/D

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